1. Field of the Invention
The present invention relates to an LSI package, an LSI element testing method, and a semiconductor device manufacturing method. More particularly, the present invention is concerned with an electrical test on an LSI element, having minute terminals, such as an LSI chip, an LSI wafer, or a chip-size package (CSP), and the manufacture of a semiconductor device having the LSI element incorporated therein.
2. Description of the Related Art
Conventionally, an LSI package is fabricated by mounting an LSI chip on a wiring board, a final test is conducted on the LSI in the state of the LSI package, the LSI package is delivered to a user, and the user incorporates the LSI package in any of various types of devices. In recent years, what is called a known good die (KGD) has increasingly adopted as a form of delivery in which an LSI chip or LSI wafer is delivered to a user as it is.
For example, in order to cope with a demand for downsizing of various types of devices, a use form called bare-chip mounting has been adopted for directly installing an LSI chip in any of various types of devices. Moreover, in order to cope with a demand for downsizing and a higher capability, a use form called a multi-chip module (MCM), a multi-chip package (MCP), or a system-in package (SIP) has been adopted for incorporation of a plurality of LSI chips in one package. In any of these forms, a known good die (KGD) is needed.
Conventionally, testing that used to be conducted after an LSI chip was fabricated in the form of any of various packages had to be conducted in the state of an LSI chip or an LSI wafer. However, the pitch between adjoining ones of terminals of the LSI chip or LSI wafer is very small (for example, 100 μm or less) and is smaller than the pitch between adjoining ones of terminals of a wiring board. The size of each of the terminals of the LSI chip or LSI wafer becomes minute in proportion to the pitch. Consequently, a testing socket or a probe card must be able to reliably come into contact with the terminals of the LSI chip or LSI wafer. The requirements for the testing socket or probe card have become very strict.
In many cases in which the KGD is needed, downsizing and high-density mounting are required. The thickness of the LSI chip or LSI wafer must therefore be decreased. As the LSI chip or LSI wafer gets thinner, more damage, including cracking, are likely to occur due to contact force or an impact stemming from manufacture.
Moreover, a problem with regard to the KGD is implementation of a burn-in test. The burn-in test (acceleration test intended to remove defective goods at an initial stage) requires a long processing time of, for example, seven to eight hours. Numerous sockets or probe cards are therefore needed in order to conduct the burn-in test on numerous LSI elements. Consequently, how to provide the burn-in test socket or probe card at a low cost is a problem that must be solved conventionally. However, as the requirements for the test socket or probe card gets stricter, it becomes harder to provide it at a low cost.
For example, Japanese Unexamined Patent Publication (Kokai) Nos. 11-064389, 2000-039452, and 2001-056347 have disclosed examples of a probe card employed in a wafer capability test. However, these probe cards are costly to manufacture. There is difficulty in preparing numerous probe cards for a burn-in test. It is impossible to deliver the probe cards together with LSI elements.
As mentioned above, LSI elements such as LSI wafers or LSI chips are becoming thinner. Therefore, the LSI elements are prone to damage. In order to attain stable electric contact for a test, considerable pressing force must be applied to the pin terminals of an LSI element and a socket. Therefore, it will presumably get harder to attain stable contact without cracking or other damage to the wafer or chip. Moreover, the terminals of the LSI element may be damaged by a probe.
There is a fear that the thus tested LSI element or, more particularly, a tested thin LSI chip may be damaged during transportation. The problem concerning an impact on the tested LSI element occurring during transportation after the delivery at a factory will become more significant.
In particular, the important functions (important factors for assessing an LSI element) which are required for testing the LSI element in order to realize a KGD are (a) assessing the capability of an LSI package to come into contact with a tester (stable electrical contact), (b) assessing the freedom in the position of a contact portion of an LSI package (whether the position of the contact portion can be determined irrespective of the arrangement of terminals or the pitch between adjoining ones thereof), (c) assessing the capability of an LSI package to protect an LSI element (to check if an LSI element is damaged or the mounting capacity of an LSI element is degraded due to a contact flaw or the like), (d) assessing a cost, (e) assessing the ease of manufacture (ease of setting an LSI package in a socket or resetting it), (f) assessing the applicability to a wide area (applicability to any chip or wafer, or a large wafer), and the like.
As for a testing method, there are, broadly, a temporary contact method and a tentative mounting method. The temporary contact method is a method of pressing an LSI element and a socket for electrical contact of the pin terminals of the LSI element with the pin terminals of the socket without fusing or joining the terminals of the LSI element and the terminals of the socket. Once pressing force is released, the terminals of the LSI element can be separated from those of the socket.
However, the temporary contact method requires application of strong pressing force to each contact point for stable electrical contact on a contact interface (for example, 10 g/pin or more). The reason why such strong force is required is to enlarge the actual contact area of the contact interface and to prevent constriction resistance. Furthermore, as the surface of each terminal has a contaminant or an oxide layered thereon, the terminal must be brought into contact with an associated terminal by breaking the layer of the contaminant or oxide.
Namely, the temporary contact method cannot deter occurrence of an electrical resistance called contact resistance. The contact resistance is attributable to two major factors described below. The first factor is the presence of constriction resistance. As an actual contact area (contact point area) is small, current is concentrated on a very small portion that is in contact with another portion. This causes the constriction resistance. When pressing force is weakened, a contact area by which terminals are in contact with one another decreases. Consequently, the constriction resistance increases, and the electrical resistance increases. Eventually, the contact becomes unstable. Therefore, a strong pressing force is needed.
The second factor is the presence of film resistance. Each of terminals has a high-resistance layer, and a contaminant such as an oxide or an organic compound layered over the surface of each of terminals is the high-resistance layer. The resistance (ranging from several tens of ohms to several megaohms) offered by the high-resistance layer is much larger than the electrical resistance (ranging from several tens of milliohms to several ohms) of the material of the terminals. Theoretically, the film resistance is proportional to the product of the thickness of the film and the resistivity of the film. However, in general, the film resistance may have significant influence on a test of the LSI element and also, the film resistance per se is unstable. Therefore, in a normal test, the film of the high-resistance layer is broken or pierced in order to bring each terminal into contact with an associated terminal. Thus, the adverse effect is prevented. A strong pressing force (for example, 10 g/pin or more) is needed in order to prevent the adverse effect of the film (to break or piece the film).
A socket employed in the temporary contact method is rigid and large as a whole. This is intended to protect an LSI element and the socket itself from being deformed due to a large load the socket produces or receives. Accordingly, the cost of the socket is high. The larger the number of pin terminals included in an LSI element is, the more severe the issue of the high cost is. For example, when pressing force of 15 g/pin is applied, if the number of pin terminals a chip has is 60, the pressing force is 0.9 kg/chip. If the number of pin terminals a chip has is 1000, the pressing force is 15 kg/chip. If a wafer is 8 inch wide and has 50000 pin terminals, the pressing force is 750 kg/chip. The socket and its housing are required to have rigidity large enough to withstand the large pressing force.
The tentatively mounting method is a method of tentatively mounting an LSI element on a wiring board, conducting a test using outer terminals of the wiring board, and then separating the LSI element from the wiring board. In this case, the pin terminals of an LSI are fused and joined with the outer terminals of the wiring board (by creating an alloy with heat). Without strong pressing force, the LSI terminals and the outer terminals of the wiring board come into electrically stable contact with each other. Unlike the temporary contact method, the housing of a socket need not be large or rigid enough to withstand strong pressing force. Only the wiring board is, substantially, needed.
However, once the pin terminals of an LSI element are fused and joined with the outer terminals of a wiring board, it is hard to peel off the terminals of the LSI element from the outer terminals of the wiring board after the completion of a test. If the terminals of the LSI element are peeled off from the outer terminals of the wiring board, the terminals of the LSI element may be damaged. This poses a problem in that the damaged LSI element cannot be mounted in an intended wiring board. When wire bonding is adopted, the remaining wires become obstacles. When bump bonding is adopted, the mounting capacity of the LSI element is impaired due to the deformation of bumps, a change in a volume, or deterioration derived from heat of a solder. When the terminals of the LSI element are peeled off from the outer terminals of the wiring board, part of a material made into the outer terminals of the wiring board is transferred (or stuck) to the terminals of the LSI element. This impairs the mounting capacity of the LSI element. In contrast, there is a concern that part of the terminals of the LSI element may be stuck on to the outer terminals of the wiring board.
When the pin terminals of an LSI element are fused and joined with the outer terminals of a wiring board, an alloy results from each pair of the terminals.
Consequently, the LSI element and the terminals of the LSI element are thermally stressed. If the coefficient of linear expansion of an LSI chip is not equal to that of a wiring board, a difference from the temperature at which the LSI chip is mounted on the wiring board (when the LSI chip is preserved at room temperature or tested) is manifested as a difference in a dimension. This causes the LSI element and wiring board to warp. Accordingly, not only the state of contact becomes unstable but also a thinned LSI chip or LSI wafer may be internally cracked. Moreover, as mentioned previously, as the joining terminals are thermally stressed, they are basically oxidized or carbonized, or have the composition thereof changed (thermally deteriorated). Compared with the terminals of an LSI element that has not been tentatively mounted, the mounting capacity of the LSI element is poor.
In short, according to the temporary contact method, terminals are readily separated from each other but strong pressing force is needed. In contrast, according to the tentative mounting method, electrical contact can be attained but it is hard to separate terminals from each other. Consequently, for prevalence of the KGD, stable electrical contact must be attained without strong force and terminals must be separable from each other. Moreover, measures must be taken for fear that after terminals are separated from each other, the terminals of an LSI element may be remarkably deformed or the mounting capacity of the LSI element later may be impaired. Furthermore, the necessity of applying high-temperature heat for joining terminals or separating terminals from each other is required to be obviated.